1. Field of the Invention
The present invention relates to drive voltage generator circuits, LCD (liquid crystal display) drivers, and liquid crystal display apparatuses. More particularly, the present invention relates to generation of drive voltages (which may be called grayscale voltages) within LCD drivers.
2. Description of the Related Art
Recent mobile electronic apparatus, such as cellular phones, often incorporate liquid crystal display apparatuses for man-machine interface. Requirements of liquid crystal display apparatuses incorporated within mobile electronic apparatuses include reduction in the circuit size and power consumption of hardware implementations. One approach for reducing the circuit size and power consumption is to incorporate a reduced number of circuitries within liquid crystal display apparatuses.
A typical liquid crystal display apparatus is composed of an LCD driver and an LCD panel. A typical LCD driver includes a grayscale voltage generator and a drive circuitry. The grayscale voltage generator generates a set of different grayscale voltages. The drive circuitry selects the grayscale voltages in response to pixel data, which are digital data representative of desired grayscale levels of the associated pixels, and outputs the selected grayscale voltages to drive the associated signal lines (or data lines) within the LCD panel.
In order to drive signal lines within an LCD panel immediately, driving the signal lines are often achieved by using buffer amplifiers incorporated within the LCD driver, which are each composed of a source follower having a gain of 1.
In a typical LCD driver configuration, as disclosed as a prior art in Japanese Laid-Open Patent Application No. P2002-108301A, buffer amplifiers are provided for respective LCD driver outputs used for providing desired drive voltages for signal lines of an LCD panel.
FIG. 1 illustrates the disclosed LCD driver structure. The disclosed LCD driver is composed of a serial-parallel shift register 1, a set of m data latches 2, a load latch circuit 3, a level shifter 4, a digital/analog (D/A) converter 5, a buffer amplifier circuit 6, and a breeder 7, m being a natural number. The buffer amplifier circuit 6 composed of a set of m buffer amplifiers 61 to 6m, outputs of which are respectively connected to m signal lines disposed within an LCD panel through a set of m outputs terminals of the LCD driver.
The shift register 1 is used to develop a set of m latch signals in response to an externally inputted shift pulse signal and transfer clock. The shift register 1 sequentially latches and shifts data bits of the shift pulse signal in synchronization with a transfer clock, and thereby develops the set of m latch signals on the parallel outputs.
The data latches 2 are each designed to latch the associated pixel data in synchronization with the associated latch signal.
The load latch circuit 3 latches the outputs of the data latches 2 in response to a load signal at the same timing.
The level shifter 4 provides level shifting between the outputs of the load latch circuit 3 and the inputs of the D/A converter 5.
The breeder 7 divides an external voltage by using a set of serially connected resistors, and thereby generates a set of n (=2k) different grayscale voltages, k being a natural number.
The D/A converter 5 selects one of the grayscale voltages for each signal line in response to the associated pixel data.
The buffer amplifiers 61 to 6m receive the associated grayscale voltages from the D/A converter 5, and provide buffering for the received grayscale voltages to develop a set of drive voltages. The drive voltages outputted from the buffer amplifiers 61 to 6m are substantially identical to the associated grayscale voltages, received from the D/A converter 5. The drive voltages are outputted to the signal lines of the LCD panel.
One drawback of this LCD driver architecture is that this LCD driver architecture requires increasing the number of the buffer amplifiers 61 to 6m for increasing the number of the outputs of the LCD driver. Increasing the screen size and/or fineness of the liquid crystal panel requires increasing the number of the signal lines of the liquid crystal panel, that is, the number of the buffer amplifiers disposed within the LCD driver. The increased number of the buffer amplifiers undesirably increases the circuit size and power consumption of the LCD driver.
In order to solve this drawback, an improved LCD driver structure has been proposed in the aforementioned Japanese Laid-Open Patent Application No. P2002-108301A, which incorporates one buffer amplifier for each grayscale voltage. This effectively allows increasing the number of LCD driver outputs without increasing the number of buffer amplifiers.
FIGS. 2 and 3 illustrate the proposed LCD driver structure. Referring to FIG. 2, the disclosed LCD driver is composed of a serial-parallel shift register 1, a set of m data latches 2, a load latch circuit 3, a level shifter 4, a decoder circuit 21, an output selector circuit 22, a buffer amplifier circuit 6, and a breeder 7; it should be noted that same numerals denote the same, similar, or equivalent elements in the specification. The disclosed LCD driver additionally includes a pixel data enable circuit 23, a pixel mode circuit 24, and an amplifier enable circuit 25.
As shown in FIG. 3, the buffer amplifier circuit 6 and the breeder 7 constitute a drive voltage generator circuit 10 that generates a set of drive voltages associated with grayscale levels, while the load latch circuit 3, the decoder circuit 21, and the output selector circuit 22 constitute a drive circuitry 20 designed to output a selected one of the drive voltages on each output terminal.
The breeder 7 is composed of a set of resistor elements R0 to Rn serially connected between the power supply VH and ground VL to generate n different grayscale voltages associated with different grayscale levels; n is the number of available grayscale levels, equal to 2k, where k is the number of data bits of each pixel data. The resistor element Rw is connected to the adjacent resistor element Rw−1 with a node TPw disposed therebetween, where w is any integer ranging from 1 to n. Such connection provides different voltages on the nodes TP1 to TPn; the voltages developed on the nodes TP1 to TPn are denoted by numerals V1 to Vn, respectively.
The buffer amplifier circuit 6 includes a set of n buffer amplifiers AM1 to AMn each having a gain of 1. The inputs of the buffer amplifiers AM1 to AMn are connected to the node TP1 to Tpn, respectively. The buffer amplifiers AM1 to AMn provide buffering for the grayscale voltages received from the nodes TP1 to TPn, respectively. The buffer amplifiers AM1 to AMn develops drive voltages on the output terminals, denoted by numerals LV1 to LV1, respectively. The drive voltages developed on the output terminals LV1 to LVn are ideally identical to the voltages V1 to Vn developed on the nodes TP1 to TPn, respectively. The drive voltages developed on the output terminals LV1 to LVn are used for driving the signal lines of the LCD panel, denoted by numeral 30 in FIG. 3.
The load latch circuit 3 is composed of a set of m latches 31 to 3m, and the decoder circuit 21 is composed of a set of m decoders 211 to 21m. Additionally, the output selector circuit 22 is composed of a set of multiplexers 221 to 22m that functions as D/A converters. The outputs of the latches 31 to 3m are connected to the inputs of the decoders 211 to 21m, respectively. The outputs of the decoders 211 to 21m are connected to the select inputs of the multiplexers 221 to 22m, respectively. The outputs of the multiplexers 221 to 22m are connected to the output terminals of the LCD driver, which are denoted by symbols OUT1 to OUTm, respectively. The output terminals OUT1 to OUTm are connected to the signal lines of the LCD panel 30.
The latches 31 to 3m latch externally inputted k-bit pixel data D1 to Dm, respectively, in synchronization with an externally inputted transfer clock CLK. The latched k-bit pixel data D1 to Dm are provided for the decoders 211 to 22m.
The decoders 211 to 22m decode the pixel data D1 to Dm.
The multiplexers 221 to 22m are each designed to select among the voltages V1 to Vn developed on the output terminals LV1 to LVn in response to the decoded pixel data D1 to Dm, respectively. When a pixel data Dv is “111111” with k=6, v being a natural number ranging from 1 to n, the multiplexer 22v selects the voltage Vn out of the voltages V1 to Vn. When a pixel data Dv is “000000”, on the other hand, the multiplexer 22v selects the voltage V1 out of the voltages V1 to Vn. The multiplexers 221 to 22m provide the selected voltages for the LCD panel 30 through the associated output terminals OUT1 to OUTm.
An advantageous feature of the LCD driver structure shown in FIG. 3 is that the LCD driver is allowed to have an increased number of output terminals without increasing the number of the buffer amplifiers; the number of the buffer amplifiers is limited to the number of the available grayscale levels.
Recent requirements include the increase in the number of available grayscale levels; however, the LCD driver structure shown in FIG. 3 suffers from a problem that the number of the buffer amplifiers is increased in proportion to the number of available grayscale levels. In order to achieve 260k-color display, for example, the LCD driver structure shown in FIG. 3 requires 64 buffer amplifiers; it should be noted that 260k-color display requires 64 grayscale levels for each R, G, B color component. The LCD driver structure shown in FIG. 3 requires 256 or 1024 buffer amplifiers for achieving natural grayscale display, involving 256 (=28) or 1024 (216) grayscale levels for each R, G, B color component. As described above, the LCD driver structure shown in FIG. 3 requires increasing the number of the buffer amplifiers for increasing the number of available grayscale levels. This undesirably increases the circuit size and power consumption of the hardware implementation of the LCD driver.
Japanese Laid Open Patent Application No. P2000-98331A discloses another LCD driver structure for reducing the number of voltage followers within an LCD driver; however, this LCD driver structure addresses achieving frame-inversion driving of LCD segment display panels with a reduced number of voltage followers, and does not provide grayscale display.